FTAPE: A fault injection tool to measure fault tolerance

The paper introduces FTAPE (Fault Tolerance And Performance Evaluator), a tool that can be used to compare fault-tolerant computers. The tool combines system-wide fault injection with a controllable workload. A workload generator is used to create high stress conditions for the machine. Faults are injected based on this workload activity in order to ensure a high level of fault propagation. The errors/fault ratio and performance degradation are presented as measures of fault tolerance

Measuring fault tolerance with the FTAPE fault injection tool

This paper describes FTAPE (Fault Tolerance And Performance Evaluator), a tool that can be used to compare fault-tolerant computers. The major parts of the tool include a system-wide fault-injector, a workload generator, and a workload activity measurement tool. The workload creates high stress conditions on the machine. Using stress-based injection, the fault injector is able to utilize knowledge of the workload activity to ensure a high level of fault propagation. The errors/fault ratio, performance degradation, and number of system crashes are presented as measures of fault tolerance

Fault Injection Techniques and Tools

Dependability evaluation involves the study of failures and errors. The destructive nature of a crash and long error latency make it difficult to identify the causes of failures in the operational environment. It is particularly hard to recreate a failure scenario for a large, complex system. To identify and understand potential failures, we use an experiment-based approach for studying the dependability of a system. Such an approach is applied not only during the conception and design phases, but also during the prototype and operational phases. To take an experiment-based approach, we must first understand a system's architecture, structure, and behavior. Specifically, we need to know its tolerance for faults and failures, including its built-in detection and recovery mechanisms, and we need specific instruments and tools to inject faults, create failures or errors, and monitor their effects

Low-Overhead Run-Time Memory Leak Detection and Recovery

Memory leaks are known to be a major cause of reliability and performance issues in software. This paper describes a run-time scheme that detects and removes memory leaks with minimal performance overhead and with no modifications to application source code. The scheme consists of a first stage where a pattern recognition technique proactively detects subtle memory leaks, followed by a more resource-intensive second stage that scans the memory space of an application and removes detected memory leaks. The pattern recognition technique in the first stage is based on the multivariate state estimation technique (MSET) which provides accurate detection of subtle memory leaks with very little overhead. The second stage is only activated when problems are identified by the first stage. For our prototype, this second stage is based on debugging and analysis tools provided by Solaris 10. Due to the low-overhead impact of the first stage, the system can be monitored for memory leaks without incurring noticeable performance degradation. We present and discuss some results from our unique proactive detection and debugging methodology.

Needs Assessment of Winooski Food Shelf Clients

Food shelves offer a unique, centralized location to engage with populations with multiple needs. Food shelf clients demonstrate poorer overall health and less access to healthcare and other social services. Winooski has a large refugee and immigrant population, whose needs may differ greatly from clients served by nearby food shelves in Chittenden County. Winooski Food Shelf visits provide opportunities to link clients to other needed health and social services. Previous studies have demonstrated efficacy in resource intervention guided by information gathered from food shelf clients. PROJECT GOAL: Assess the greatest health and social needs for clientele of the Winooski Food Shelf and make recommendations based on data gathered.https://scholarworks.uvm.edu/comphp_gallery/1283/thumbnail.jp

Modelling amorphous computations with transcription networks

The power of electronic computation is due in part to the development of modular gate structures that can be coupled to carry out sophisticated logical operations and whose performance can be readily modelled. However, the equivalences between electronic and biochemical operations are far from obvious. In order to help cross between these disciplines, we develop an analogy between complementary metal oxide semiconductor and transcriptional logic gates. We surmise that these transcriptional logic gates might prove to be useful in amorphous computations and model the abilities of immobilized gates to form patterns. Finally, to begin to implement these computations, we design unique hairpin transcriptional gates and then characterize these gates in a binary latch similar to that already demonstrated by Kim et al. (Kim, White & Winfree 2006 Mol. Syst. Biol. 2, 68 (doi:10.1038/msb4100099)). The hairpin transcriptional gates are uniquely suited to the design of a complementary NAND gate that can serve as an underlying basis of molecular computing that can output matter rather than electronic information